1. Field of the Invention
The present invention relates to a data processing apparatus having a main memory and a plurality of memory banks.
2. Description of the Related Art
One conventional data processing apparatus will be described below with reference to FIGS. 1 and 2 of the accompanying drawings. As shown in FIG. 1, the data processing apparatus has main memory 101, n memory banks 1021, through 102n, CPU (Central Processing Unit) 103, and register circuit 104.
Main memory 101 has a number of successive memory spaces each having a series of main addresses xe2x80x9c000xe2x80x9d, xe2x80x9c001xe2x80x9d, . . . , xe2x80x9c010xe2x80x9d set thereto. Memory banks 1021 through 102n also have a plurality of successive memory spaces, and the memory spaces of each memory bank have common successive bank addresses xe2x80x9c011xe2x80x9d, xe2x80x9c012xe2x80x9d, . . . , xe2x80x9c100xe2x80x9d set thereto. CPU 103 is connected to main memory 101 and memory banks 1021 through 102n by address bus 105 and a data bus (not shown), and reads data stored in main memory 101 successively in the order of the main addresses and data stored in memory banks 1021 through 102n successively in the order of the bank addresses. Register circuit 104 is connected to main memory 101, memory banks 1021 through 102n, and CPU 103, and is controlled by CPU 103 to store the bank number of one of memory banks 1021 through 102n.
In the conventional data processing apparatus, a series of computer program instructions for CPU 103 are stored in main memory 101 and memory banks 1021 through 102n. CPU 103 reads the computer program instructions and executes data processing according to the read computer program instructions.
As shown in FIG. 2 of the accompanying drawings, main memory 101 stores, at arbitrary main addresses, a first bank switching instruction, a second bank switching instruction, . . . , an nth bank switching instruction for branching readout destinations for CPU 103 to respective memory banks 1021, 1022, . . . , 102n. Memory banks 1021, 1022, . . . , 102n store, at respective final bank addresses, a first main return instruction, a second main return instruction, . . . , an nth main return instruction for branching readout destinations for CPU 103 to respective main addresses next to those main addresses where the first bank switching instruction, the second bank switching instruction, . . . , the nth bank switching instruction are stored in main memory 101.
When CPU 103 reads the series of computer program instructions from the main memory 101 and memory banks 1021 through 102n, since stored data in main memory 101 are successively read from the first main address, the bank switching instructions are read from certain main addresses.
In the illustrated conventional data processing apparatus, the first bank switching instruction which is read first designates the first bank address in memory bank 1021, and hence the readout destination for CPU 103 is branched to the first bank address in memory bank 1021. At this time, CPU 103 stores the memory bank number xe2x80x9c1xe2x80x9d corresponding to the first bank switching instruction in register circuit 104. Therefore, only memory bank 1021, becomes valid, and memory banks 1022 through 102nbecome invalid. As a result, CPU 103 reads stored data in memory bank 1021, successively from its bank addresses beginning with the first bank address until finally it reads the main return instruction. Since the main return instruction stored in memory bank 1021, designates the main address next to the main address where the first bank switching instruction is stored in main memory 101, the readout destination for CPU 103 becomes the main address next to the main address where the first bank switching instruction is stored in main memory 101.
Similarly, CPU 103 reads data from main memory 101, and each time CPU 103 reads a bank switching instruction, it reads stored data in a corresponding memory bank. When the readout of data from memory bank 102n, is completed, the processing returns to the readout of data from main memory 101.
The conventional data processing apparatus use common bank addresses shared by memory banks 1021 through 102n. When CPU 103 stores a memory bank number corresponding to a bank switching instruction in register circuit 104, plural memory banks 102 become valid one at a time. Therefore, a small number of bank addresses can be assigned to many memory spaces.
However, since it is necessary to store the first through nth bank switching instructions which designate first through nth memory banks memory banks 1021 through 102n, respectively, in main memory 101, some of the memory spaces in main memory 101 are consumed for storing these bank switching instructions.
Furthermore, the final bank addresses of first through nth memory banks memory banks 1021 through 102n are required to set therein the first through nth main return instructions which designate the main addresses next to the main addresses where the first through nth bank switching instructions are stored in main memory 101. The process of setting the first through nth main return instructions in the final bank addresses is complex.
In addition, main memory 101 is unable to store considerably long successive data therein because the first through nth bank switching instructions are stored at arbitrary main addresses.
It is an object of the present invention to provide a data processing apparatus which minimizes the consumption in a main memory of memory spaces for bank switching instructions, is not required to set main return instructions inherent in respective memory banks, and is capable of storing considerably long successive data in the main memory.
According to a first aspect of the present invention, a data processing apparatus has a main memory, first through nth memory banks, a data processing circuit, and a bank switching means.
The main memory has a plurality of successive memory spaces each with a series of main addresses set thereto and stores in an arbitrary memory space thereof a bank switching instruction which designates a first bank address of the first memory bank. The first through nth memory banks have a plurality of successive memory spaces with a series of bank addresses set commonly thereto, and the first through (n-1)th memory banks having virtual spaces where no stored data is present in respective final bank addresses thereof. The nth memory bank stores in the memory space represented by the final bank address thereof a main return instruction which designates a particular main address of the main memory.
The data processing circuit reads stored data in the memory spaces successively from the main addresses beginning with a head address. The data processing circuit switches the readout destination therefor to the head bank address of the first memory bank and reads data successively from the first memory bank beginning with the head address. When the readout destination in the first memory bank reaches the bank address of the virtual space, the readout destination is switched to the second memory bank by the bank switching means, and the data processing circuit reads data successively from the second memory bank beginning with the head address. The above operation is repeated until the readout destination is switched to the nth memory bank. When the main return instruction is read from the final bank address of the nth memory bank, the readout destination returns to a particular main address of the main memory. Having read all the stored data in the memory banks, the data processing circuit reads data subsequent to the particular main address of the main memory.
According to a second aspect of the present invention, the main memory stores in an arbitrary memory space thereof a bank switching instruction which designates a particular bank address of the first memory bank, the first through (n-1)th memory banks have virtual spaces where no stored data is present in respective particular bank addresses thereof, and the nth memory bank stores in the memory space represented by a particular bank address thereof a main return instruction which designates a particular main address of the main memory.
When the data processing circuit reads stored data in the main memory up to a particular main address, the data processing circuit reads data from the memory banks up to the respective particular bank addresses. When the readout of the data is completed, the data processing circuit reads data subsequent to the particular main address of the main memory.
According to a third aspect of the present invention, the main memory stores in arbitrary memory spaces thereof bank switching instructions which designate a plurality of different bank addresses of the first memory bank, the first through (n-1)th memory banks have virtual spaces where no stored data is present in respective bank addresses thereof, and the nth memory bank stores in the memory spaces represented by the bank addresses thereof main return instructions which designate different particular main addresses of the main memory.
When the data processing circuit reads stored data in the main memory up to a first particular main address, the data processing circuit reads data from the memory banks up to the respective first particular bank addresses. When the readout of the data is completed, the data processing circuit reads stored data from the first particular main address to the second particular main address of the main memory, and reads stored data from the first particular bank address to the second particular bank address of each of the memory banks. The same operation is repeated until the stored data at the final address of the main memory is read.
According to the present invention, even though there are not as many bank switching instructions as the number of main banks in the main memory, the readout destination for the data processing circuit can be shifted successively from the main memory to the memory banks. Therefore, the memory spaces in the main memory can effectively be utilized.
When the data processing circuit reads the main return instruction from the nth memory bank, the data processing circuit returns the readout destination to the main address next to the main address where the bank switching instruction is stored in the main memory. Consequently, the memory spaces in the main memory can more effectively be utilized.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.